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M1AFS600-PQ208 Datasheet, PDF (84/334 Pages) Microsemi Corporation – Fusion Family of Mixed Signal FPGAs
Device Architecture
CLK1
ADDR1
DIN1
CLK2
tAS tAH
A0
tDS tDH
D0
tWRO
ADDR2
A0
A2
D2
tAS tAH
A1
DOUT2
(flow-through)
DOUT2
(Pipelined)
tCKQ1
Dn
Dn
D0
tCKQ2
Figure 2-54 • One Port Write / Other Port Read Same
CLK
tCKH
tCYC
tCKL
A3
D3
A4
D1
D0
RESET
DOUT|RD
Dm
tRSTBQ
Dn
Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.
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Revision 4