SH7708 Datasheet, PDF (99/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 4 Exception Handling
4.1 Overview
4.1.1 Features
Exceptions are deviations from normal program execution that require special handling. The
processor responds to an exception by aborting execution of the current instruction (execution is
allowed to continue to completion in all interrupt requests) and passing control from the
instruction stream to the appropriate user-written exception handling routine. Here, all exceptions
other than resets and interrupts will be called general exceptions. There are thus three types of
exceptions: resets, general exceptions, and interrupts.
4.1.2 Register Configuration
A register with an undefined initial value should be initialized by software. Table 4.1 lists the
registers used for exception handling.
Table 4.1 Register Configuration
Register
Abbr. R/W Size
TRAPA exception register TRA
R/W Longword
Exception event register EXPEVT R/W Longword
Interrupt event register INTEVT R/W Longword
Initial Value
Undefined
Power-on reset:
H'000
Manual reset: H'020
Undefined
Address
H'FFFFFFD0
H'FFFFFFD4
H'FFFFFFD8
4.2 Exception Handling Function
4.2.1 Exception Handling Flow
Usually the contents of the program counter (PC) and status register (SR) are saved in the saved
program counter (SPC) and saved status register (SSR), respectively, and execution of the
exception handler is invoked from a vector address. The return from exception handler (RTE)
instruction is issued by the exception handler routine at the completion of the routine, restoring the
contents of the PC and SR to return to the processor status at the point of interruption and the
address where the exception occurred.
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