SH7708 Datasheet, PDF (195/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.8 Overview of the Watchdog Timer (WDT)
9.8.1 Block Diagram of the WDT
Figure 9.4 shows a block diagram of the WDT.
Standby
cancellation
Internal
reset
request
Interrupt
request
Standby
control
WDT
Reset
control
Interrupt
control
Clock selection
Overflow
Divider
Clock selector
Clock
WTCSR
WTCNT
Bus interface
Standby
mode
Peripheral
clock
WTCSR: Watchdog timer control/status register
WTCNT: Watchdog timer counter
Internal bus
Figure 9.4 Block Diagram of the WDT
9.8.2 Register Configurations
The WDT has two registers that select the clock, switch the timer mode, and perform other
functions. Table 9.5 shows the WDT register.
Table 9.5 Register Configuration
Name
Abbreviation R/W Size
Initial Value Address
Watchdog timer counter WTCNT
R/W* R: byte;
W: word*
H'00
H'FFFFFF84
Watchdog timer
control/status register
WTCSR
R/W* R: byte;
W: word*
H'00
H'FFFFFF86
Note: * Write with a word access. Write H'5A and H'A5, respectively, in the upper bytes. Byte or
longword writes are not possible. Read with a byte access.
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