SH7708 Datasheet, PDF (390/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Figure 13.6 shows an example of SCI transmit operation in asynchronous mode.
1
Serial
data
TDRE
Start
bit
0 D₀
Parity Stop Start
Data bit bit bit
D₁
D₇ 0/1 1 0 D₀
Parity Stop
Data _bit bit 1
D₁
D₇
0/1
1
Idle
(mark)
state
TEND
TXI interrupt
request
TXI interrupt
handler writes
data to SCTDR
and clears TDRE
bit to 0
TXI interrupt
request
TEI interrupt
request
1 frame
Figure 13.6 SCI Transmit Operation in Asynchronous Mode (Example: 8-Bit Data with
Parity and One Stop Bit)
Receiving Serial Data (Asynchronous Mode): Figure 13.7 shows a sample flowchart for
receiving serial data. The procedure for receiving serial data after enabling the SCI for reception
is:
1. Receive error handling and break detection: If a receive error occurs, read the ORER, PER and
FER bits in SCSSR to identify the error. After executing the necessary error handling, clear
ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1.
When a framing error occurs, the RxD pin can be read to detect the break state.
2. SCI status check and receive-data read: Read the serial status register (SCSSR), check that
RDRF is set to 1, then read receive data from the receive data register (SCRDR) and clear
RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from
0 to 1.
3. To continue receiving serial data: Read the RDRF and SCRDR bits and clear RDRF to 0
before the stop bit of the current frame is received.
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