SH7708 Datasheet, PDF (335/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.4.2 Status Flag Clear Timing
The status flag can be cleared by writing a 0 from the CPU. Figure 11.9 shows the timing.
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
TCR address
UNF, ICPF
Figure 11.9 Status Flag Clear Timing
11.4.3 Interrupt Sources and Priorities
The TMU produces underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception
source register (INTEVT) for these interrupts and interrupt handling occurs according to the
codes.
The relative priorities of channels can be changed using the interrupt controller (see section 6,
Interrupt Controller) and section 4, Exception Handling. Table 11.3 lists TMU interrupt sources.
Table 11.3 TMU Interrupt Sources
Channel
0
1
2
2
Interrupt Source
TUNI0
TUNI1
TUNI2
TICPI2
Description
Priority
Underflow interrupt 0 High
Underflow interrupt 1
Underflow interrupt 2
↑↓
Input capture interrupt 2 Low
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