SH7708 Datasheet, PDF (223/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit: 15
14
Bit name: WAITSEL* —
Initial value:
0
0
R/W: W
R
13
A6IW1
1
R/W
12
A6IW0
1
R/W
11
A5IW1
1
R/W
10
A5IW0
1
R/W
9
A4IW1
1
R/W
8
A4IW0
1
R/W
Bit:
7
6
5
4
3
2
1
0
Bit name: A3IW1 A3IW0 A2IW1 A2IW0 A1IW1 A1IW0 A0IW1 A0IW0
Initial value:
1
1
1
1
1
1
1
1
R/W: R/W
R/W R/W R/W R/W R/W R/W R/W
Note: * SH7708R A-mask version only
Bits 15 and 14 —Reserved: These bits always read 0. The write value should always be 0.
Bit 15—WAIT Signal Sampling Timing Specification (WAITSEL) [A-mask version only]
Bit 15: WAITSEL
0
1
Description
WAIT signal is sampled at rise of CKIO
In this case, the WAIT signal should be input synchronously
WAIT signal is sampled at fall of CKIO
In this case, the WAIT signal can be input asynchronously
(Initial value)
Bits 2n + 1, 2n—Area n (6–0) Intercycle Idle Specification (AnIW1, AnIW0): These bits specify
the number of idles inserted between bus cycles when switching between physical space area n (6–
0) to another space or between a read access to a write access in the same physical space.
Bit 2n + 1: AnIW1
0
1
Bit 2n: AnIW0
0
1
0
1
Description
No idle cycles
1 idle cycle inserted
2 idle cycles inserted
3 idle cycles inserted
(Initial value)
205