SH7708 Datasheet, PDF (171/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.7 Hardware Standby Mode
The hardware standby mode is provided only in the SH7708S and SH7708R. This mode is not
supported in emulator.
8.7.1 Transition to Hardware Standby Mode
Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode,
all modules except those operating on an RTC clock are halted, as in the standby mode entered on
execution of a SLEEP instruction.
Hardware standby mode differs from standby mode as follows.
1. Interrupts and manual resets are not accepted.
2. The TCLK clock output is fixed low.
3. The TMU does not operate.
4. In the SH7708S and SH7708R, the RTC continues to operate even if power is not supplied to
power supply pins other than those for RTC power. In this case, all output pins go to the non-
drive state. With the SH7708, it is not possible to supply power only to the RTC power
supply.
Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows.
1. In standby mode
The clock remains stopped and the chip enters the hardware standby state. Acceptance of
interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts.
2. During WDT operation when standby mode is canceled by an interrupt
The chip enters hardware standby mode after standby mode is canceled and the CPU resumes
operation.
3. In sleep mode
The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes
operation.
4. During PLL standby (see section 9.6 for the PLL standby function)
The chip enters hardware standby mode after forced implementation of the PLL OFF state.
Hold the CA pin low in hardware standby mode.
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