SH7708 Datasheet, PDF (256/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the fall of
the clock.
If the setup time and hold times with respect to the falling edge of the clock are not satisfied, the
value sampled at the next falling edge is used.
CKIO
Wait states inserted
by WAIT signal
T1
Tw
Tw
Tw
T2
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
WAIT
BS
Figure 10.12 Basic Interface Wait State Timing
(Wait State Insertion by WAIT Signal, WAITSEL = 1)
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