SH7708 Datasheet, PDF (149/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.2.10 Break Data Mask Register B (BDMRB)
Bit: 31
30
29
28
27
26
25
24
Bit name: BDM31 BDM30 BDM29 BDM28 BDM27 BDM26 BDM25 BDM24
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
19
18
17
16
Bit name: BDM23 BDM22 BDM21 BDM20 BDM19 BDM18 BDM17 BDM16
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
14
13
12
11
10
Bit name: BDM15 BDM14 BDM13 BDM12 BDM11 BDM10
Initial value: —
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W
9
BDM9
—
R/W
8
BDM8
—
R/W
Bit:
Bit name:
Initial value:
R/W:
7
BDM7
—
R/W
6
BDM6
—
R/W
5
BDM5
—
R/W
4
BDM4
—
R/W
3
BDM3
—
R/W
2
BDM2
—
R/W
1
BDM1
—
R/W
0
BDM0
—
R/W
Break data mask register B (BDMRB) is a 32-bit read/write register that determines which of the
bits in the break address set in BDRB are masked. BDMRB is not initialized by a reset.
BDMRB Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31 to BDMB0): These bits specify
whether bits B31–B0 (BDB31 to BDB0) of the channel B break data set in BDRB are masked. Set
the same values in BDMB15–BDMB8 as are set in BDMB7–BDMB 0.
Bits 31–0: BDMBn
Description
0
Channel B break data bit BDBn is included in the break condition.
1
Channel B break data bit BDBn is masked and therefore not included
in the break condition.
n = 31 to 0
Notes: 1. When the data bus value is contained in the break conditions, specify the operand size.
2. For byte data, set the same data in bits 0–7 and bits 8–15 of BDRB and BDMRB.
3. Bits 31–16 of BDRB and BDMRB are ignored for byte and word sizes.
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