SH7708 Datasheet, PDF (429/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 14.7 Maximum Bit Rates for Frequencies (Smart Card Interface Mode)
Pφ (MHz)
7.1424
10.00
10.7136
13.00
14.2848
16.00
18.00
Maximum Bit Rate (Bit/s)
9600
13441
14400
17473
19200
21505
24194
N
n
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The bit rate error is found as follows:
Error(%)
=
(
1488
×
Pφ
2^2n–1 ×
B
×
(N
+
1)
×
10⁶
–
1)
×
100
Table 14.8 shows the relationship between transmit/receive clock register set values and output
states on the smart card interface.
Table 14.8 Register Set Values and SCK Pin
Register Value
SCK Pin
Setting SMIF C/A CKE1 CKE0 Output
State
1*¹
1
0
0
0
Port
Determined by setting of port
register SPB1IO and SPB1DT
bits
1
0
0
1
SCK (serial clock) output state
2*²
1
1
0
0
Low output Low output state
1
1
0
1
SCK (serial clock) output state
3*²
1
1
1
0
High output High output state
1
1
1
1
SCK (serial clock) output state
Notes: 1. The SCK output state changes as soon as the CKE0 bit is modified. The CKE1 bit
should be cleared to 0.
2. The clock duty remains constant despite stopping and starting of the clock by
modification of the CKE0 bit.
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