SH7708 Datasheet, PDF (60/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.11 System Control Instructions (cont)
Instruction
Operation
Code
LDC.L @Rm+,
R4_BANK
(Rm) → R4_BANK,
Rm + 4 → Rm
0100mmmm11000111
LDC.L @Rm+,
R5_BANK
(Rm) → R5_BANK,
Rm + 4 → Rm
0100mmmm11010111
LDC.L @Rm+,
R6_BANK
(Rm) → R6_BANK,
Rm + 4 → Rm
0100mmmm11100111
LDC.L @Rm+,
R7_BANK
(Rm) → R7_BANK,
Rm + 4 → Rm
0100mmmm11110111
LDS Rm,MACH
Rm → MACH
0100mmmm00001010
LDS Rm,MACL
Rm → MACL
0100mmmm00011010
LDS Rm,PR
Rm → PR
0100mmmm00101010
LDS.L @Rm+,MACH (Rm) → MACH, Rm + 4 → Rm 0100mmmm00000110
LDS.L @Rm+,MACL (Rm) → MACL, Rm + 4 → Rm 0100mmmm00010110
LDS.L @Rm+,PR
(Rm) → PR, Rm + 4 → Rm
0100mmmm00100110
LDTLB
PTEH/PTEL → TLB
0000000000111000
NOP
No operation
0000000000001001
PREF @Rm
(Rm) → cache
0000mmmm10000011
RTE
Delayed branch,
0000000000101011
SSR/SPC → SR/PC
SETS
1→S
0000000001011000
SETT
1→T
0000000000011000
SLEEP
Sleep
0000000000011011
STC SR,Rn
SR → Rn
0000nnnn00000010
STC GBR,Rn
GBR → Rn
0000nnnn00010010
STC VBR,Rn
VBR → Rn
0000nnnn00100010
STC SSR,Rn
SSR → Rn
0000nnnn00110010
STC SPC,Rn
SPC → Rn
0000nnnn01000010
STC R0_BANK,Rn R0_BANK→ Rn
0000nnnn10000010
STC R1_BANK,Rn R1_BANK→ Rn
0000nnnn10010010
STC R2_BANK,Rn R2_BANK→ Rn
0000nnnn10100010
STC R3_BANK,Rn R3_BANK→ Rn
0000nnnn10110010
Note: * The number of cycles until the sleep state is entered.
Privileged
Mode
Cycles T Bit
√
1
—
√
1
—
√
1
—
√
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
√
1
—
—
1
—
—
1
—
√
4
—
—
1
—
—
1
1
√
4*
—
√
1
—
—
1
—
√
1
—
√
1
—
√
1
—
√
1
—
√
1
—
√
1
—
√
1
—
42