SH7708 Datasheet, PDF (228/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

and pseudo-SRAM, specifies address multiplexing, and controls refresh. This enables direct
connection of DRAM, synchronous DRAM and pseudo-SRAM without external circuits.
MCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode. Bits TPC1–TPC0, RCD1–RCD0, TRWL1–TRWL0, TRAS1–TRAS0, BE, SZ,
AMX1–AMX0, and EDOMODE are written to in the initialization after a power-on reset and are
not then modified again. When RFSH and RMODE are written to, write the same values to the
other bits. When using DRAM, pseudo-SRAM, and synchronous DRAM, do not access areas 2
and 3 until this register is initialized.
Bit:
Bit name:
R/W:
15
TPC1
0
R/W
14
TPC0
0
R/W
13
RCD1
0
R/W
12
RCD0
0
R/W
11
10
9
TRWL1 TRWL0 TRAS1
0
0
0
R/W R/W R/W
8
TRAS0
0
R/W
Bit: 7
Bit name: —
Initial value: 0
R/W: R
6
5
4
3
2
1
0
BE
SZ AMX1 AMX0 RFSH RMODE EDO
MODE
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
Bits 15 and 14—RAS Precharge Time (TPC1, TPC0): When DRAM interface is selected as
connected memory, the TPC bits set the minimum number of cycles until the next RAS assertion
after RAS negation. When synchronous DRAM interface is selected, they set the minimum
number of cycles until output of the next bank-active command after precharge. When pseudo-
SRAM interface is selected, they set the minimum number of cycles until the next CE assertion
after CE negation.
Bit 15: TPC1
0
1
Bit 14: TPC0
0
1
0
1
Normally
1 cycle (Initial value)
2 cycles
3 cycles
4 cycles
Description
Immediately after Self-Refresh
2 cycles (Initial value)
5 cycles
8 cycles
11 cycles
210