SH7708 Datasheet, PDF (345/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

12.2.9 Second Alarm Register (RSECAR)
The second alarm register (RSECAR) is an 8-bit read/write register, and an alarm register
corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the
ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among the
RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an RTC alarm interrupt is generated.
The range that can be set is 00–59 (decimal) + ENB bit. Errant operation will result if any other
value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields
are not initialized by a power-on reset or manual reset, or in standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: ENB
10 seconds
1 second
Initial value: 0
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R/W: R/W R/W R/W R/W R/W R/W R/W R/W
12.2.10 Minute Alarm Register (RMINAR)
The minute alarm register (RMINAR) is an 8-bit read/write register, and an alarm register
corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB
bit is set to 1, a comparison with the RMINCNT value is performed. From among the RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR registers, the counter and alarm register
comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an
RTC alarm interrupt is generated.
The range that can be set is 00–59 (decimal) + ENB bit. Errant operation will result if any other
value is set.
The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are
not initialized by a power-on reset or manual reset, or in standby mode. Contents are retained in a
manual reset and in standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: ENB
10 minutes
1 minute
Initial value: 0
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—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
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