SH7708 Datasheet, PDF (176/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.2 Overview of the CPG
9.2.1 CPG Block Diagram
A block diagram of the on-chip clock pulse generator is shown in figure 9.1(SH7708, SH7708S)
and figure 9.2(SH7708R).
CAP1
CKIO
Cycle = Bcyc
CAP2
XTAL
EXTAL
Crystal
oscillator
Clock pulse generator
PLL circuit 1
(× 1, 2, 4)
PLL circuit 2
(× 1, 4)
Divider 1
×1
× 1/2
× 1/4
Divider 2
×1
× 1/2
× 1/4
Internal
clock (Iφ)
Cycle = Icyc
Peripheral
clock (Pφ)
Cycle = Pcyc
MD2
MD1
MD0
CPG control unit
Clock frequency
control circuit
Standby control
circuit
FRQCR
STBCR
Standby
control
Bus interface
Internal bus
FRQCR: Frequency control register
STBCR: Standby control register
Figure 9.1 Block Diagram of Clock Pulse Generator(SH7708, SH7708S)
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