SH7708 Datasheet, PDF (127/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.1.3 Pin Configuration
Table 6.1 shows the INTC pin configuration.
Table 6.1 Pin Configuration
Name
Nonmaskable interrupt input pin
Interrupt input pins
Bus request output pin
Abbreviation I/O
NMI
I
IRL3–IRL0 I
IRQOUT
O
Description
Input of nonmaskable interrupt request
signal
Input of interrupt request signals
(maskable by I3–I0 in SR)
Output of signal that notifies external
devices that an interrupt or memory
refresh request has occurred
6.1.4 Register Configuration
The INTC has the three registers listed in table 6.2.
Table 6.2 Register Configuration
Name
Abbr.
Initial
R/W Value*¹ Address
Interrupt control register
ICR
R/W *²
H'FFFFFEE0
Interrupt priority level setting register A IPRA
R/W H'0000 H'FFFFFEE2
Interrupt priority level setting register B IPRB
R/W H'0000 H'FFFFFEE4
Notes: 1. Initialized by a power-on reset or manual reset.
2. H'8000 when the NMI pin is high, H'0000 when the NMI pin is low.
Access
Size
16
16
16
6.2 Interrupt Sources
There are three types of interrupt sources: NMI, IRL, and on-chip supporting modules. Each
interrupt has a priority level (0–16) with 0 the lowest and 16 the highest. Priority level 0 masks an
interrupt.
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