SH7708 Datasheet, PDF (187/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Do not set the internal clock frequency lower than the CKIO pin frequency.
5. The frequency of the peripheral clock (Pφ) becomes:
• The product of the frequency of the CKIO pin, the frequency multiplication ratio of
PLL circuit 1, and the division ratio of divider 2 when the clock operating mode is 0–2
or 7.
• The product of the frequency of the CKIO pin and the division ratio of divider 2 when
the clock operating mode is 3 and 4.
• The peripheral clock frequency should not be set higher than the frequency of the CKIO
pin, higher than 30 MHz(SH7708, SH7708S) / 33.3 MHz(SH7708R), or lower than 1/4
(SH7708, SH7708S) / 1/8(SH7708R) the internal clock (Iφ).
6. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the
multiplication ratio of PLL circuit 1. This frequency should be equal to or lower than 60
MHz(SH7708, SH7708S) / 100 MHz(SH7708R).
7. × 1, × 2, × 3* or × 4 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2, × 1/3*,
and × 1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency
control register. The on/off state of PLL circuit 2 is determined by the mode. × 3 multiplication
of PLL circuit 1 and × 1/3 of dividers 1 and 2 are not supported in emulator.
Note: SH7708R only
8. For more in formation about the range of usable freguencies for each clock operating mode,see
table 9.4.
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