SH7708 Datasheet, PDF (145/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.2.3 Break ASID Register A (BASRA)
Bit:
Bit name:
Initial value:
R/W:
7
BASA7
—
R/W
6
BASA6
—
R/W
5
BASA5
—
R/W
4
BASA4
—
R/W
3
BASA3
—
R/W
2
BASA2
—
R/W
1
BASA1
—
R/W
0
BASA0
—
R/W
Break ASID register A (BASRA) specifies the ASID that serves as the break condition for channel
A. It is compared to the ASID field of the MMU's PTEH register. BASRA is an 8-bit read/write
register. It is not initialized by a reset.
Bits 7 to 0—Break ASID A7 to 0 (BASA7 to BASA0): These bits store the ASID (bits 7 to 0) that
is the channel A break condition.
7.2.4 Break ASID Register B (BASRB)
BASRB is the break ASID register for channel B. The bit configuration is the same as for
BASRA.
7.2.5 Break Address Mask Register A (BAMRA)
Bit: 7
6
5
4
Bit name: —
—
—
—
Initial value: 0
0
0
0
R/W: R/W R/W R/W R/W
3
2
1
0
— BASMA BAMA1 BAMA0
0
—
—
—
R/W R/W R/W R/W
Break address mask register A (BAMRA) is an 8-bit read/write register that specifies which bits in
the break ASID specified in BASRA and which bits in the break address specified in BARA are
masked. It is not initialized by a reset.
Bits 7 to 3—Reserved: These bits always read 0. The write value should always be 0.
Bit 2—Break ASID Mask A (BASMA): Indicates whether the bits of the channel A breakpoint
ASID7 to ASID0 (BASA7 to BASA0) set in BASRA are masked.
Bit 2: BASMA
0
1
Description
BASRA not masked; all bits included in break condition.
All BASRA bits masked; ASID not included in break condition.
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