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SH7708 Datasheet, PDF (534/633 Pages) Renesas Technology Corp – SuperH™ RISC engine
T1
Tw
Tw
TB2
TB1
Tw
TB2
T2
T2
CKIO
tAD
A25–A4
A3–A0
tCSD1
CSn
tRWD
RD/WE
tRSD
RD
D31–D0
tBSD
tBSD
tAD
tAD
tAH
tCSD2 tRWH
tRSD tAH tRSD
tRSD
tRDH1
tRWD
tAH
tRSD tRWH
tRDS1
tRDH1
tRDS1
tRDH1
tRDH1
tBSD
tBSD
BS
,,,,,,,,,, WAIT
tWTS tWTH
tWTS tWTH
tWTS tWTH
tWTS tWTH
Note: In the write cycle, the basic bus cycle is performed.
Figure 17.21 Burst ROM Bus Cycle (2 Waits)
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