SH7708 Datasheet, PDF (357/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

written 1. When the PEF bit become 1, the periodic interrupt occurs. PEF bit should be set to 0
when setting PES bits or when the interrupt occurs.
PES set, PEF clear Set RCR2.PES bits and 0 clear PEF
Wait for period
designated by PES
PEF clear
0 clear PEF bit
Figure 12.7 Using the Periodic Interrupt Function
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