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| SH7708 Datasheet, PDF (473/633 Pages) Renesas Technology Corp – SuperH™ RISC engine | |||
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16.3.5 Burst ROM Timing
T1
TB2
TB1
TB2
TB1
TB2
TB1
T2
CKIO
tAD
A25âA4
tAD
A3âA0
tCSD1
CSn
tRWD
RD/WE
tRSD tRSD tAH
RD
tRDH1
tRDS
D31âD0
tBSD
tBSD
BS
WAIT
tAD
tAD
tAH
tCSD2 tRWH
tRDH1
tRWD
tRSD
tAH
tRSD tRWH
tRDS1
tRDH1
tBSD
tBSD
tWTS tWTH
Note: In the write cycle, the basic bus cycle is performed.
Figure 16.20 Burst ROM Bus Cycle (No Wait)
455
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