SH7708 Datasheet, PDF (374/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit 1: SPB0IO
0
1
Description
The SPB0DT bit value is not output to the TxD pin.
The SPB0DT bit value is output to the TxD pin.
(Initial value)
Bit 0—Serial Port Break Data (SPB0DT): Specifies the serial port I/O data. Use the SPB0IO bit to
specify input or output of TxD pin. See the description of SPB0IO for details. SPB0DT bit is
output to the TxD pin when specified as output. The RxD pin value is read from the SPB0IO bit
regardless of the SPB0IO bit value. The initial value is undefined.
Bit 0 : SPB0DT
0
1
Description
I/O data level is low.
I/O data level is high.
(Initial value)
Block diagrams of the SCI I/O port pins are shown in figures 15.2 to 15.4 in section 15, I/O Ports.
13.2.9 Bit Rate Register (SCBRR)
The bit rate register (SCBRR) is an 8-bit register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a reset and in
module standby or standby mode. Each channel has independent baud rate generator control, so
different values can be set in the two channels.
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
Asynchronous mode: N = [Pφ/(64 × 2^{2n – 1} × B)] × 10⁶ – 1
Synchronous mode: N = [Pφ/(8 × 2^{2n – 1} × B)] × 10⁶ – 1
B: Bit rate (bit/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 13.3.)
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