SH7708 Datasheet, PDF (179/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.2.2 CPG Pin Configuration
Table 9.1 lists the CPG pins and their functions.
Table 9.1 Clock Pulse Generator Pins and Functions
Pin Name
Symbol
Mode control
pins
MD0
MD1
MD2
Crystal I/O pins XTAL
(clock input pins) _EXTAL
Clock I/O pin
CKIO
Capacitor
connection pins
for PLL
CAP1
CAP2
I/O Description
I Set the clock operating mode.
I
I
O Connects a crystal oscillator.
I Connects a crystal oscillator. Also used to input an external
clock.
I/O Inputs or outputs an external clock. Level can be fixed during
output.
I Connects capacitor for PLL circuit 1 operation (recommended
value 470 pF).
I Connects capacitor for PLL circuit 2 operation (recommended
value 470 pF).
9.2.3 CPG Register Configuration
Table 9.2 shows the CPG register configuration.
Table 9.2 Register Configuration
Register Name
Initial
Abbreviation R/W Value*
Address
Access Size
Frequency control register FRQCR
R/W H'0102
H'FFFFFF80 16
Note: * Initialized by a power-on reset via the RESET pin. Register contents are retained in a
power-on reset initiated by the WDT.
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