SH7708 Datasheet, PDF (76/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

3.2 Register Description
There are five registers for MMU processing. These are all peripheral module registers, so they are
located in address space area P4 and can only be accessed from privileged mode by specifying the
address. These registers consist of:
1. The page table entry register high (PTEH) register residing at address H'FFFFFFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual
address at which the exception is generated in the case of an MMU exception or address error
exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address,
but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified
by software. As the ASID, software sets the number of the currently executing process. The
VPN and ASID are recorded in the TLB by the LDTLB instruction.
2. The page table entry register low (PTEL) register residing at address H'FFFFFFF4, and used to
store the physical page number and page management information to be recorded in the TLB
by the LDTLB instruction. The contents of this register are only modified in response to a
software command.
3. The translation table base register (TTB) residing at address H'FFFFFFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB
automatically. TTB is available to software for general purposes.
4. The TLB exception address register (TEA) register residing at address H'FFFFFFFC, which
stores the virtual address corresponding to a TLB or address error exception. This value
remains valid until the next exception or interrupt.
5. The MMU control register (MMUCR) residing at address H'FFFFFFF0, which makes the
MMU settings described in figure 3.3. Any program that modifies MMUCR should reside in
the P1 or P2 area.
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