SH7708 Datasheet, PDF (126/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.1.2 Block Diagram
Figure 6.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRL3–IRL0
Input
control
4
4
TMU
RTC
SCI
WDT
REF
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request/
refresh request)
Priority
identifier
Com-
parator
Interrupt
request
SR
3210
CPU
ICR
IPR
IPRA–IPRB
Bus
interface
TMU:
RTC:
SCI:
WDT:
REF:
ICR:
IPRA–IPRB:
SR:
INTC
Timer unit
Realtime clock unit
Serial communication interface
Watch dog timer
Memory refresh controller section of the bus state controller
Interrupt control register
Interrupt priority level setting registers A–B
Status register
Figure 6.1 INTC Block Diagram
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