SH7708 Datasheet, PDF (387/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Initialize
Clear TE and RE bits in SCSCR to 0
Set CKE1 and CKE0 bits in SCSCR
(TE and RE bits are 0)
(1)
Select transmit/receive
(2)
format in SCSMR
Set value to SCBRR
(3)
Wait
Has a 1-bit
No
interval elapsed?
Yes
Set TE and RE bits in SCSCR to 1
and set RIE, TEIE, and MPIE bits ⁽⁴⁾
End
Note: Numbers in parentheses refer to the preceding procedure.
Figure 13.4 Sample Flowchart for SCI Initialization
Transmitting Serial Data (Asynchronous Mode): Figure 13.5 shows a sample flowchart for
transmitting serial data. The procedure for transmitting serial data is:
1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that
the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear
TDRE to 0.
2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if
it reads 1); if so, write data in SCTDR, then clear TDRE to 0.
3. To output a break at the end of serial transmission: Clear the SPB0DT bit in the SCSPTR, set
the SPB0IO bit to 1 and then clear the TE bit to 0 in SCSCR.
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