SH7708 Datasheet, PDF (62/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Notes: 1. The table shows the minimum number of execution cycles. The actual number of
instruction execution cycles will increase in cases such as the following:
• When there is contention between an instruction fetch and data access
• When the destination register in a load (memory-to-register) instruction is also used
by the next instruction
2. With the addressing modes using displacement (disp) listed below, the assembler
descriptions in this manual show the value before scaling (×1, ×2, or ×4) is performed.
This is done to clarify the operation of the chip. For the actual assembler descriptions,
refer to the individual assembler notation rules.
@ (disp:4, Rn) ; Register-indirect with displacement
@ (disp:8, Rn) ; GBR-indirect with displacement
@ (disp:8, PC) ; PC-relative with displacement
disp:8, disp:12 ; PC-relative
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