SH7708 Datasheet, PDF (282/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Single Write: The basic timing chart for write access is shown in figure 10.28. In a single write
operation, following the Tr cycle in which ACTV command output is performed, a WRITA
command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data
is output at the same time as the write command. For the write with auto-precharge command,
precharging of the relevant bank is performed in synchronous DRAM after completion of the write
command, and therefore no command can be issued for the same bank until precharging is
completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle
Trwl is also added as a wait interval until precharging is started following the write command.
Issuance of a new command for the same bank is postponed during this interval. The number of
Trwl cycles can be specified by the TRWL bit in MCR.
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