SH7708 Datasheet, PDF (147/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 5 and 4—Instruction Fetch/Data Access Select A (IDA1 and IDA0): These bits select whether
to break channel A on instruction fetch and/or data access cycles.
Bit 5: IDA1
0
1
Bit 4: IDA0
0
1
0
1
Description
No conditions compared
(Initial value)
Break on instruction fetch cycle
Break on data access cycle
Break on either instruction fetch or data access cycle
Bits 3 and 2—Read/Write Select A (RWA1 and RWA0): These bits select whether to break
channel A on read and/or write cycles.
Bit 3: RWA1
0
1
Bit 2: RWA0
0
1
0
1
Description
No conditions compared
Break on read cycles
Break on write cycles
Break on both read and write cycles
(Initial value)
Bits 1 and 0—Operand Size Select A (SZA1 and SZA0): These bits select the bus cycle operand
size as a channel A break condition.
Bit 1: SZA1
0
1
Bit 0: SZA0
0
1
0
1
Description
Operand size is not a break condition
Break on byte access
Break on word access
Break on longword access
(Initial value)
7.2.8 Break Bus Cycle Register B (BBRB)
BBRB is the break bus cycle register for channel B. The bit configuration is the same as for
BBRA.
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