SH7708 Datasheet, PDF (5/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Preface
The SH7708, SH7708S, and SH7708R(SH7708 Series) use a RISC (reduced instruction set
computer) type CPU to achieve high-performance computational processing. Also incorporating
the peripheral functions required for system configuration plus power-down features essential for
microcontroller application systems, the SH7708 Series is a new-generation RISC microcontroller
(SuperH™ RISC engine).
The SH7708 Series has a RISC type instruction set, with basic instructions executed in one state,
offering a drastic improvement in instruction execution speed. It also has an on-chip 32-bit
multiplier (producing a 64-bit result) capable of high-speed multiply-and-accumulate operations.
The SH7708 Series’s instructions are upward-compatible with those of the SH-1 and SH-2,
facilitating migration from these series to the SH7708 Series.
SH7708R is completely pin compatible with the SH7708S. On-chip supporting modules that
enable a user system to be configured with a minimum of components include oscillation circuits,
an interrupt controller (INTC), timers, a realtime clock (RTC), and a serial communication
interface (SCI). A user break controller (UBC) is provided as an on-chip module supporting
program development, allowing easy configuration of a simple debugger.
On-chip cache memory improves CPU processing performance, and a built-in memory
management unit (MMU) performs address translation between a 4-gigabyte virtual space and
physical space. An on-chip bus state controller (BSC) provides more efficient external memory
access, and enables direct connection to synchronous DRAM, DRAM, and pseudo-SRAM without
the need for glue logic.
This hardware manual describes the hardware of the SH7708 Series. Details of instructions can be
found in the programming manual.
Note: * SuperH is a trademark of Hitachi, Ltd.
Related Manuals
SH7708Series instructions
SH-3/SH-3E/SH3-DSP Programming Manual
Please consult your Hitachi sales representative for details of development environment system.