SH7708 Datasheet, PDF (34/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Register values after a reset are shown in table 2.1.
Table 2.1 Initial Register Values
Type
General registers
Control registers
Registers
R0 to R15
SR
GBR, SSR, SPC
VBR
System registers
MACH, MACL, PR
PC
Note: Initialized by a power-on reset or manual reset.
Initial Value
Undefined
MD bit = 1, RB bit = 1, BL bit = 1, I3–
I0 = 1111 (H'F), reserved bits = 0,
others undefined
Undefined
H'00000000
Undefined
H'A0000000
2.1.2 General Registers
There are 16 general registers, designated R0 to R15 (figure 2.3). General registers R0 to R7 are
banked registers, with a different R0–R7 register bank (R0_BANK0–R7_BANK0 or
R0_BANK1–R7_BANK1) being accessed according to the processor mode. For details, see
section 2.1.1, Privileged Mode and Banks.
31
R0*^1, *²
R1*²
R2*²
R3*²
R4*²
R5*²
R6*²
R7*²
R8
R9
R10
R11
R12
R13
R14
R15
General Registers
0
Notes:
1. R0 functions as an index register in the indexed
register-indirect addressing mode and indexed
GBR-indirect addressing mode. In some instructions,
only R0 can be used as the source register or
destination register.
2. R0–R7 are banked registers.
In privileged mode, SR.RB specifies which banked
registers are accessed as general registers
(R0_BANK0–R7_BANK0 or R0_BANK1–R7_BANK1).
Figure 2.3 General Registers
16