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SH7708 Datasheet, PDF (206/633 Pages) Renesas Technology Corp – SuperH™ RISC engine | |||
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⢠Direct interface to pseudo-SRAM
 Supports burst operation (static column mode)
 Auto-refresh and self-refresh
⢠ROM burst interface
 Insertion of wait states controllable through software
 Register setting control of burst transfers
⢠PCMCIA direct-connection interface
 Insertion of wait states controllable through software
 Burst operation (page mode)
 Bus sizing function for I/O bus width (little-endian mode only)
⢠Fine refreshing control
 Supports refresh operation immediately after self-refresh operation in low-power DRAM
by means of refresh counter overflow interrupt function
⢠Refresh counter can be used as an interval timer
 Interrupt request generated at compare-match
 Interrupt request generated at refresh counter overflow
10.1.2 Block Diagram
Figure 10.1 shows a block diagram of the bus state controller.
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