SH7708 Datasheet, PDF(110/633 Page) Renesas Technology Corp – SuperH™ RISC engine

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SH7708 Datasheet, PDF (110/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

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â¢ TLB protection exception

ï£§ Conditions: When a hit access violates the TLB protection information (PR bits) shown

below:

PR

Privileged mode

User mode

00

Only read enabled No access

01

Read/write enabled No access

10

Only read enabled Only read enabled

11

Read/write enabled Read/write enabled

ï£§ Operations: The virtual address (32 bits) that caused the exception is set in TEA and the

corresponding virtual page number (22 bits) is set in PTEH (31â10). The ASID of PTEH

indicates the ASID at the time the exception occurred. The way that generated the

exception is set in the RC bits in MMUCR.

The PC and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception

occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1

and a branch occurs to PC = VBR + H'0100.

â¢ Address error

ï£§ Conditions:

a. Instruction fetch from odd address (4n + 1, 4n + 3)

b. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)

c. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2,

4n + 3)

d. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF.

ï£§ Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC

and SR of the instruction that generated the exception are saved to the SPC and SSR,

respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the

exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in

SR are set to 1 and a branch occurs to PC = VBR + H'0100.

For details see section 3.5.5, Processing Flow in Event of MMU Exception.

â¢ Unconditional trap

ï£§ Conditions: TRAPA instruction executed

ï£§ Operations: The exception is a processing-completion type, so the PC of the instruction

after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA

instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA

instruction is quadrupled and set in TRA(9â0). H'160 is set in EXPEVT. The BL, MD, and

RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100.

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