SH7708 Datasheet, PDF (509/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

16.3.10 Peripheral Module Signal Timing
Table 16.11 Peripheral Module Signal Timing (Conditions: V_CC = 3.3 ± 0.3 V, Ta = 0 to
75°C)
Module Item
Symbol
TMU,
RTC
Timer input setup time
Timer clock input setup
time
t_CLKS1
t_CKS
Timer clock Single edge t_TCKWH
pulse width _{Both edges tTCKWL}
Oscillation settling time t_ROSC
SCI Input clock Asyn-
t_Scyc
cycle
chronous
syn-
chronous
Input clock rise time
t_SCKr
Input clock fall time
t_SCKf
Input clock pulse width t_SCKw
Transmit data delay time t_TXD
Receive data setup time t_RXS
(synchronous)
Receive
data hold
time (syn-
chronous)
Clock input t_RXH
Clock
output
t_RXH
–15
Min Max
20 —
20 —
1.5 —
2.5 —
—3
4—
6—
— 1.5
— 1.5
0.4 0.6
— 100
100 —
100 —
0—
–30
Min Max
15 —
15 —
1.5 —
2.5 —
—3
4—
6—
— 1.5
— 1.5
0.4 0.6
— 100
100 —
100 —
0—
–60
Min Max Unit Figure
12 — ns 16.54,
12 — ns ^16.55
1.5 —
2.5 —
—3
4—
6—
tcyc
tcyc
S 16.61
tcyc 16.62–
16.64
tcyc
— 1.5 tcyc
— 1.5 tcyc
0.4 0.6 tscyc
— 100 ns
100 — ns
100 — ns
0 — ns
Port Output data delay time t_PORTD — 20 — 17 — 15 ns
Input data setup time t_PORTS 20 — 15 — 12 — ns
Input data hold time
t_PORTH 10 —
8—
5 — ns
491