SH7708 Datasheet, PDF (255/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

When software wait insertion is specified by WCR2, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 10.11. A 2-cycle wait is specified as a software
wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, the
WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle. The WAIT signal is
sampled on the rising edge of the clock. WAIT is a synchronous signal.
CKIO
A25 to A0
CSn
RD/WR
Wait states inserted
by WAIT signal
T1
Tw
Tw
Tw
T2
Read
RD
D31 to D0
Write
WEn
D31 to D0
WAIT
BS
Figure 10.11 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal)
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