SH7708 Datasheet, PDF (118/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

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65 4 3 2 1 0
— ^{... ... ... ... ... ... ... ... ...} RA 0 CF * WT CE
RA: RAM bit. Indicates the cache operation mode.
1 = 4 kbytes cache/4 kbytes cache (RAM mode)
0 = 8 kbytes cache (normal mode)
0: Always set to 0 when setting the register.
CF: Cache flush bit. Invalidates all cache entries. 1 = flush (clears the V, U, and LRU bits
of all entries to 0).
Always reads 0. Write-back to external memory is not performed when the cache is
flushed.
—: Reserved bits. Always read 0; and the write value should always be 0.
WT: Write-through bit. Indicates the cache’s operating mode for areas P0, U0, and P3.
1 = write-through mode, 0 = write-back mode.
CE: Cache enable bit. Indicates whether the cache function is used.
1 = cache used, 0 = cache not used.
CB: P1 area write-back/write-through switching bit
1 = write-back mode, 0 = write-through mode
Note:SH7708:Reserved bit
SH7708S,SH7708R:CB
Figure 5.2 CCR Register Configuration
5.3 Cache Operation
5.3.1 Searching the Cache
If the cache is enabled, whenever instructions or data in memory are accessed the cache will be
searched to see if the desired instruction or data is in the cache. Figure 5.3 illustrates the method
by which the cache is searched. The cache is a physical cache and holds physical addresses in its
address section.
Entries are selected using bits 10–4 of the address (virtual) of the access to memory and the
address tag of that entry is read. In parallel to reading of the address tag, the virtual address is
translated to a physical address in the MMU. The physical address after translation and the
physical address read from the address section are compared. The address comparison uses all four
ways in normal mode. In RAM mode, two ways (way 0 and way 1) are used in the address
comparison. When the comparison shows a match and the selected entry is valid (V = 1), a cache
hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0),
a cache miss occurs. Figure 5.3 shows a hit on way 1.
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