SH7708 Datasheet, PDF (425/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

The operating sequence is:
1. The data line is high impedance when not in use and is fixed high with a pull-up resistor.
2. The transmitting side starts one frame of data transmission. The data frame starts with a start
bit (Ds, low level). The start bit is followed by eight data bits (D0–D7) and a parity bit (Dp).
3. On the smart card interface, the data line returns to high impedance after this. The data line is
pulled high with a pull-up resistor.
4. The receiving side checks parity. When the data is received normally with no parity errors, the
receiving side then waits to receive the next data. When a parity error occurs, the receiving
side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving
station returns the signal line to high impedance after outputting the error signal for a specified
period. The signal line is pulled high with a pull-up resistor.
5. The transmitting side transmits the next frame of data unless it receives an error signal. If it
does receive an error signal, it returns to step 2 to re-transmit the erroneous data.
14.3.4 Register Settings
Table 14.3 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or
0 must be set to the indicated value. The settings for the other bits are described below.
Table 14.3 Register Settings for the Smart Card Interface
Register
SCSMR
SCBRR
SCSCR
SCTDR
SCSSR
Address
H'FFFFFE80
H'FFFFFE82
H'FFFFFE84
H'FFFFFE86
H'FFFFFE88
Bit 7
C/A
BRR7
TIE
TDR7
TDRE
Bit 6
0
BRR6
RIE
TDR6
RDRF
SCRDR H'FFFFFE8A RDR7 RDR6
SCSCMR H'FFFFFE8C —
—
Note: Dashes indicate unused bits.
Bit 5
1
BRR5
TE
TDR5
ORER
RDR5
—
Bit 4
O/E
BRR4
RE
TDR4
FER/
ERS
RDR4
—
Bit 3
1
BRR3
0
TDR3
PER
RDR3
SDIR
Bit 2
0
BRR2
0
TDR2
TEND
RDR2
SINV
Bit 1
CKS1
BRR1
CKE1
TDR1
0
RDR1
—
Bit 0
CKS0
BRR0
CKE0
TDR0
0
RDR0
SMIF
407