SH7708 Datasheet, PDF (235/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bits 5 and 4—Area 6 Address OE/WE Assert Delay (A6TED1, A6TED0): These bits specify the
address to OE/WE assert delay time for the PCMCIA interface connected to area 6.
Bit 5: A6TED1
0
1
Bit 4: A6TED0
0
1
0
1
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
(Initial value)
Bits 3 and 2—Area 5 OE/WE Negate Address Delay (A5TEH1, A5TEH0): These bits specify the
OE/WE negate address delay time for the PCMCIA interface connected to area 5.
Bit 3: A5TEH1
0
1
Bit 2: A5TEH0
0
1
0
1
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
(Initial value)
Bits 1 and 0—Area 6 OE/WE Negate Address Delay (A6TEH1, A6TEH0): These bits specify the
OE/WE negate address delay time for the PCMCIA interface connected to area 6.
Bit 1: A6TEH1
0
1
Bit 0: A6TEH0
0
1
0
1
Description
0.5 cycle delay
1.5 cycle delay
2.5 cycle delay
3.5 cycle delay
(Initial value)
10.2.8 Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address
bus and is a virtual 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3.
SDMR settings must be made before synchronous DRAM is accessed.
Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the
value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM
mode register by writing in address X + Y. Since A0 of the synchronous DRAM is connected to
A2 of the chip and A1 of the synchronous DRAM is connected to A3 of the chip, the value
actually written to the synchronous DRAM is the X value shifted two bits right. For example,
when H'0230 is written to the SDMR register of area 2, random data is written to the address
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