SH7708 Datasheet, PDF (129/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 6.3 IRL3–IRL0 Pins and Interrupt Levels
IRL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
IRL2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IRL1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
IRL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt Priority Level
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Interrupt Request
Level 15 interrupt request
Level 14 interrupt request
Level 13 interrupt request
Level 12 interrupt request
Level 11 interrupt request
Level 10 interrupt request
Level 9 interrupt request
Level 8 interrupt request
Level 7 interrupt request
Level 6 interrupt request
Level 5 interrupt request
Level 4 interrupt request
Level 3 interrupt request
Level 2 interrupt request
Level 1 interrupt request
No interrupt request
A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels
sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that
no transient level on the IRL pin change is detected. In standby mode, as the peripheral clock is
stopped, noise cancellation is performed using the 32.768 kHz clock for the RTC instead.
Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed
in standby mode.
The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the
interrupt handling starts. However, the priority level can be changed to a higher one.
The interrupt mask bits (I3–I0) in the status register (SR) are not affected by IRL interrupt
handling.
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