SH7708 Datasheet, PDF (264/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Burst Access: In addition to the normal DRAM access mode in which a row address is output in
each data access, a high-speed page mode is also provided in cases where consecutive accesses are
made to the same row. This mode allows fast access to data by outputting the row address only
once, then changing only the column address for each subsequent access. Normal access or burst
access using high-speed page mode can be selected by means of the burst enable (BE) bit in MCR
and DCR. The timing for burst access using high-speed page mode is shown in figure 10.17.
In burst transfer, 4 (longword access) or 16 (cache fill or cache write-back) bytes of data are burst-
transferred in a 16-bit bus size. With a 32-bit bus size, 16 bytes of data are burst-transferred (cache
fill or cache write-back). In a 16-byte burst transfer (cache fill), the first access comprises a
longword that includes the data requiring access. The remaining accesses are performed on 16-
byte boundary data that includes the relevant data. In burst transfer (cache write-back), sequential
writing is performed if first-to-last order for 16-byte boundary data.
246