SH7708 Datasheet, PDF (266/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

EDO Mode: In DRAM, an extended data out (EDO) mode is also provided in which, once the
CAS signal is asserted while the RAS signal is asserted, even if the CAS signal is negated, data is
output to the data bus until the CAS signal is next asserted. (This is in addition to the mode in
which data is output to the data bus only while the CAS signal is asserted in a data read cycle.) In
the SH7708 Series, the EDO mode bit (EDOMODE) in MCR enables selection, for area 3 DRAM
only, of either normal access/burst access using high-speed page mode or EDO mode normal
access/burst access. EDO mode normal access is shown in figure 10.18, and burst access in figure
10.19.
In EDO mode, the timing for data output to the data bus in a read cycle is extended as far as the
next assertion of the CAS signal. This delays the data latch timing by 1/2 cycle to the rising edge
of the CKIO clock, enabling the DRAM access time to be increased.
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