SH7708 Datasheet, PDF (254/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2
settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a
software wait is inserted in accordance with that specification. For details, see section 10.2.4, Wait
Control Register 2 (WCR2).
The specified number of Tw cycles is inserted as wait cycles using the basic interface wait timing
shown in figure 10.10.
CKIO
T1
Tw
T2
A25 to A0
CSn
RD/WR
Read
RD
D31 to D0
Write
WEn
D31 to D0
BS
Figure 10.10 Basic Interface Wait Timing (Software Wait Only)
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