SH7708 Datasheet, PDF (21/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 1.1 SH7708 Series Features (cont)
Item
Memory
management
unit (MMU)
Cache memory
Interrupt
controller
(INTC)
User break
controller
(UBC)
Features
• 4 Gbytes of address space, 256 address spaces (8-bit ASID)
• Supports single virtual memory mode and multiple virtual memory mode
• Paging system
• Supports multiple page sizes: 1 or 4 kbytes
• 128-entry, 4-way set associative TLB
• Supports software selection of replacement method and random-replacement
algorithms
• Contents of TLB are directly accessible by address mapping
• Choice of operating mode
 Normal mode (8-kbyte cache)
 RAM mode (4-kbyte cache + 4-kbyte RAM)
• Mixed instruction/data, 128 entries, 16-byte block length
 4-way set associative (8-kbyte cache)
 2-way set associative (4-kbyte cache)
• Selectable write method (write-back/write-through), LRU (least recently used)
replacement algorithm
• Single-stage write-back buffer
• Contents of TLB can be accessed directly by address mapping (can be used
as on-chip memory)
• 5 external interrupt pins (NMI, IRL0 to IRL3)
• Encoded input of 15 external interrupt sources via pins IRL0 to IRL3
• On-chip peripheral interrupts: priority levels set for each module
• Supports debugging by user break interrupts
• 2 break channels
• Addresses, data values, type of access, and data size can all be set as break
conditions
• Supports a sequential break function
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