SH7708 Datasheet, PDF (546/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

17.3.7 Synchronous DRAM Timing
CKIO
A25–A16
A12 or A10
A15–A0
CSn
RD/WR
RAS
CAS
DQMxx
D31–D0
BS
T_r
T_c1
T_c2
(T_pc)
t_AD
t_AD
t_AD
t_AD
,,,,,, ^{Row address}
t_AD
t_AD
Row
Read A
address command
t_AD
t_AD
Row
address
Column address
t_CSD1
t_CSD1
t_RWD
t_RWD
t_RASD2
t_RASD2
t_DQMD
t_CASD2
t_CASD2
t_DQMD
t_RDS2 t_RDH2
t_BSD
t_BSD
CKE
(High)
Figure 17.34 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)
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