SH7708 Datasheet, PDF (156/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

7.3.5 Examples of Use
Register settings, set conditions, and states in which the set conditions are matched, are as follows:
1. Instruction fetch cycle break condition setting (independent channel A and B conditions)
BRCR = H'0400: Independent channel A and B conditions, post-execution for channel A,
pre-execution for channel B
Channel A:
BASRA = H'80:
BARA = H'00000404:
BAMRA = H'00:
BBRA = H'0014:
ASID H'80
Address H'00000404
Address mask H'00
Bus cycle, instruction fetch (post-execution),
read (operand size not included in conditions)
Channel B:
BASRB = H'70:
ASID H'70
BARB = H'00008010: Address H'00008010
BAMRB = H'02:
Address mask H'02
BBRB = H'0014:
Bus cycle, instruction fetch (pre-execution),
read (operand size not included in conditions)
BDRB = H'00000000: Data H'00000000
BDMRB = H'00000000: Data mask H'00000000
A user break is generated after execution of the instruction at address H'00000404 with
ASID = H'80, or before execution of instructions at addresses H'00008000 to H'000083FE with
ASID = H'70.
2. Instruction fetch cycle break condition setting (independent channel A and B conditions)
BRCR = H'0080: Channel A → channel B sequential conditions, pre-execution for channel
A, pre-execution for channel B
Channel A:
BASRA = H'80:
BARA = H'00037226:
BAMRA = H'00:
BBRA = H'0016:
ASID H'80
Address H'00037226
Address mask H'00
Bus cycle, instruction fetch (pre-execution),
read, word
Channel B:
BASRB = H'70:
ASID H'70
BARB = H'0003722E: Address H'0003722E
BAMRB = H'00:
Address mask H'00
BBRB = H'0016:
Bus cycle, instruction fetch (pre-execution),
read, word
BDRB = H'00000000: Data H'00000000
BDMRB = H'00000000: Data mask H'00000000
A user break is generated before execution of the instruction at address H'0003722E with
138