SH7708 Datasheet, PDF (522/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

17.3.2 Control Signal Timing
Table 17.6 Control Signal Timing (V_CC = 3.15–3.6 V, Ta = –20 to + 75°C)
–60*²
Item
Symbol
Min
Max
Unit
Figure
RESET pulse width
RESET setup time
t_RESW
t_RESS
20
—
tcyc
17.11, 17.13,
23
—
ns
17.15
RESET hold time
t_RESH
2
—
ns
BREQ setup time
t_BREQS
12
—
ns
BREQ hold time
t_BREQH
3
—
ns
BREQ reset setup time
t_BREQRS
17
—
ns
BREQ reset hold time
t_BREQRH
16
—
ns
MD reset setup time
t_MDRS
20
—
tcyc
17.12
MD reset hold time
t_MDRH
16
—
ns
NMI setup time*¹
t_NMIS
15
—
ns
17.13
IRL3–IRL0 setup time*¹
t_IRLS
10
—
ns
NMI hold time
t_NMIH
4
—
ns
IRL3–IRL0 hold time
t_IRLH
4
—
ns
IRQOUT delay time
t_IRQOD
—
12
ns
17.14
BACK delay time
t_BACKD
—
12
ns
17.15, 17.16
STATUS1, STATUS0 delay time t_STD
—
16
ns
Bus tri-state delay time 1
t_BOFF1
0
16
ns
Bus tri-state delay time 2
t_BOFF2
0
16
ns
Bus buffer on time 1
t_BON1
0
16
ns
Bus buffer on time 2
t_BON2
0
16
ns
Notes: 1. RESET, NMI, and IRL3 to IRL0 are asynchronous. Changes are detected at the clock
fall when the setup shown is used. When the setup cannot be used, detection can be
delayed until the next clock fall.
2. Upper limit of external bus clock is 60 MHz.
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