SH7708 Datasheet, PDF (314/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

CKIO
T1
T2 Twait T1
T2 Twait T1
T2
A25 to A0
CSm
CSn
BS
RD/WR
RD
D31 to D0
Area m read
Area n space read
Area n space write
Area m inter-access wait specification Area n inter-access wait specification
Figure 10.50 Waits between Access Cycles
10.3.10 Bus Arbitration
When a bus release request (BREQ) is received from an external device, buses are released after
the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not
released during burst transfers for cache fills. In the case of multiple bus cycles generated because
the data bus width is smaller than the access size—for example, in longword access to 8-bit-wide
memory—bus arbitration is not performed between bus cycles. At the negation of BREQ, BACK
is negated and bus use is restarted. See Appendix B, Pin States, for the pin status when the bus is
released.
The SH7708 Series sometimes needs to retrieve a bus it has released. For example, when memory
generates a refresh request or an interrupt request internally, the SH7708 Series must perform the
appropriate processing. The SH7708 Series has a bus request signal (IRQOUT) for this purpose.
When it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus
release request receive the assertion of the IRQOUT signal and negate the BREQ signal to release
the bus. The SH7708 Series retrieves the bus and carries out the processing.
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