SH7708 Datasheet, PDF (272/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

CKIO
TRc TRr1 TRrw TSR1 TSR1 TSR2 (Tpc) (Tpc)
RAS
CASxx
RD/WR
CS2 or CS3
(High)
Figure 10.22 DRAM Self-Refresh Cycle Timing
Power-On Sequence: For DRAM after powering on, a minimum wait time of 100 µs or 200 µs,
or more during which no access can be performed, should be provided, followed by the prescribed
number (usually 8 or more) of dummy CAS-before-RAS refresh cycles. As the bus state controller
does not perform any special operations for a power-on reset, the power-on sequence must be
carried out by the initialization program executed after a power-on reset.
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