SH7708 Datasheet, PDF (275/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Address Multiplexing: Synchronous DRAM can be connected without external multiplexing
circuitry in accordance with the address multiplex specification bits AMX1 and AMX0 in MCR.
Table 10.13 shows the relationship between the address multiplex specification bits and the bits
output at the address pins.
A25–A16 and A0 are not multiplexed; the original values are always output at these pins.
When A0, the LSB of the synchronous DRAM address, is connected to the SH7708 Series, it
performs longword address specification. Connection should therefore be made in this order:
connect pin A0 of the synchronous DRAM to pin A2 of the SH7708 Series, then connect pin A1
to pin A3. Table 10.14 shows the example of correspondence between SH7708 Series and
synchronous DRAM address pins.
Table 10.13 Relationship between SZ, AMX, and Address Multiplex Output
Setting
External Address Pins
AMX1 AMX0 Output Timing A1 to A8 A9 A10 A11 A12 A13 A14 A15
0
0
Column address A1 to A8 A9 A10 A11 L/H*¹ A21*² A14 A15
Row address A9 to A16 A17 A18 A19 A20 A21*² A22 A23
0
1
Column address A1 to A8 A9 A10 A11 L/H*¹ A22*² A14 A15
Row address A10 to A17 A18 A19 A20 A21 A22*² A23 A24
1
0
Column address A1 to A8 A9 A10 A11 L/H*¹ A23*² A14 A15
Row address A11 to A18 A19 A20 A21 A22 A23*² A24 A25
1
1
Column address A1 to A8 A9 L/H*¹ A19*² A12 A13 A14 A15
Row address A9 to A16 A17 A18 A19*² A20 A21 A22 A23
Notes: 1. L/H is a bit used in the command specification; it is fixed at L or H according to the
access mode.
2. Bank address specification.
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