SH7708 Datasheet, PDF (236/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

H'FFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to
the SDMR register. When H'0230 is written to the SDMR register of area 3, random data is
written to the address H'FFFE000 (address Y) + H'08C0 (value X) or H'FFFFE8C0. As a result,
H'0230 is written to the SDMR register. The range for value X is H'000 to H'0FFC.
Address bits
Bit: 31
12
11
10
9
8
Bit name:
SDMR address
Initial value: —
·············
—
—
—
—
—
R/W: —
·············
—
W*
W*
W
W
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: —
—
—
—
—
—
—
—
R/W: W
W
W
W
W
W
—
—
Note: Depending on the type of synchronous DRAM.
10.2.9 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTSCR) is a 16-bit read/write register that specifies the
refresh cycle, whether to generate an interrupt, and the cycle of that interrupt. RTSCR is initialized
to H'0000 by a power-on reset, but is not initialized by a manual reset or in standby mode.
Note:
The method for writing to RTCOR is different from that for general registers to prevent
inadvertent overwriting. Using a word transfer instruction, place B'10100101 in the upper
byte and the write data in the lower byte. For details, see section 10.2.13, Cautions on
Accessing Refresh Control Related Registers.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Bit:
Bit name:
Initial value:
R/W:
7
CMF
0
R/W
6
CMIE
0
R/W
5
CKS2
0
R/W
4
CKS1
0
R/W
3
CKS0
0
R/W
2
OVF
0
R/W
1
OVIE
0
R/W
0
LMTS
0
R/W
Bits 15 to 8—Reserved: These bits always read 0.
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