SH7708 Datasheet, PDF (105/633 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 4.3 Exception Codes (cont)
Exception Type
Exception Event
General interrupt requests
(cont)
External hardware interrupts (cont):
IRL3–IRL0 = 1001
IRL3–IRL0 = 1010
IRL3–IRL0 = 1011
IRL3–IRL0 = 1100
IRL3–IRL0 = 1101
IRL3–IRL0 = 1110
Peripheral module interrupt:
TMU0
TUNI0
TMU1
TUNI1
TMU2
TUNI2
TICPI2
RTC
ATI
PRI
CUI
SCI
ERI
RXI
TXI
TEI
WDT
ITI
REF
RCMI
ROVI
Note: Exception codes H'120, H'140, and H'3E0 are reserved.
Exception Code
H'320
H'340
H'360
H'380
H'3A0
H'3C0
H'400
H'420
H'440
H'460
H'480
H'4A0
H'4C0
H'4E0
H'500
H'520
H'540
H'560
H'580
H'5A0
4.2.5 Exception Request Masks
When the BL bit in SR is cleared to 0, exceptions and interrupts are accepted.
If a general exception event occurs when the BL bit in SR is 1, the CPU’s internal registers are set
to their post-reset state, other module registers retain their contents prior to the general exception,
and a branch is made to the same address (H'A0000000) as for a reset.
If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted
until the BL bit is cleared to 0 by software. For reentrant exception handling, the SPC and SSR
must be saved and the BL bit in SR cleared to 0.
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